This invention relates in general to a built-in self test for an integrated circuit, and in specific to a built-in self test for content adjustable memory.
Built-in self tests (BISTs) are commonly implemented within integrated circuits (e.g., chips) of the prior art to test the accuracy of such chips. For example, BISTs have been implemented in the prior art to allow for testing the accuracy of random access memory (RAM). However, many chips utilize content addressable memory (CAM). As is well known in the art, RAM memory, such as static RAM (SRAM) or dynamic RAM (DRAM), is commonly implemented for storing data. As is also well known in the art, a CAM structure is typically a RAM that comprises associated circuitry (e.g., a comparator) for comparing received data with data stored therein very quickly. As an example, cache structures implemented for processors typically include a translation look-aside buffer (TLB), which is generally a large CAM structure. Generally, when an instruction being executed by the processor requests access to memory (e.g., to read from or write to a memory address), the cache""s TLB receives a virtual address for such memory access request and translates the virtual address to a physical address.
However, prior art designs have not implemented a BIST for testing a CAM structure. That is, a BIST for testing a CAM structure has not been utilized in prior art chips. Instead, CAM structures are typically tested in the prior art using off-chip software programs. Utilizing such off-chip testing programs of the prior art to test CAM structures typically requires a large amount of testing time. For example, an undesirably long time is typically required to test a TLB of the prior art.
In testing prior art chips that include CAM structures, a significant portion of the test time is typically required to test the CAM structure. For instance, testing a CAM structure utilizing testing procedures of the prior art may require thousands of clock cycles. As an example of a typical method used for testing a CAM structure, suppose a CAM structure is implemented on a chip for a TLB. To test the cells of the CAM used for the TLB, the entire CAM array may first be initialized to 0. Thus, the chip must be set into a mode in which a virtual address of all 0""s can be input for each entry of the TLB. After each of the entries in the TLB are set to a virtual address of all 0""s (e.g., virtual address =000000000), then a test address of all 0""s and a walking 1 may be utilized to test the TLB""s entries. For instance, a test address having a 1 only in its most significant bit position (e.g., test address 100000000) may be input to the TLB to ensure that the TLB does not translate this test address as matching with one of its entries (i.e., to ensure that a xe2x80x9cmissxe2x80x9d or xe2x80x9cnon-matchxe2x80x9d occurs for every entry of the TLB. If a xe2x80x9chitxe2x80x9d (or xe2x80x9cmatchxe2x80x9d) is detected for any entry, then it is determined that the CAM structure failed (i.e., that the CAM structure is defective). After testing each entry for a test address having a 1 for its most significant bit position, the 1 is shifted or xe2x80x9cwalkedxe2x80x9d over to the next lower bit of the test address (e.g., test address=010000000) and is input to the TLB. The test is repeated on the TLB with the 1 being walked through each bit position of the test address, and if a xe2x80x9chitxe2x80x9d (or xe2x80x9cmatchxe2x80x9d) is detected for any of the test addresses then it is determined that the CAM structure has failed.
Once the test has been completed for a walking 1, the test is typically repeated by initializing every cell of the CAM array to 1 and testing the CAM with a test address having all 1""s and a walking 0. For example, each of the entries in the TLB may be set to a virtual address of all 1""s (e.g., virtual address=111111111), then a walking 0 can be utilized to test the TLB""s entries. For instance, a test address having a 0 only in its most significant bit position (e.g., test address=011111111) may be input to the TLB to ensure that the TLB does not translate this test address as matching with one of its entries (i.e., to ensure that a xe2x80x9cmissxe2x80x9d or xe2x80x9cnon-matchxe2x80x9d occurs for every entry of the TLB. If a xe2x80x9chitxe2x80x9d (or xe2x80x9cmatchxe2x80x9d) is detected for any entry, then it is determined that the CAM structure failed (i.e., that the CAM structure is defective). After testing each entry for a test address having a 0 for its most significant bit position, the 0 is shifted or xe2x80x9cwalkedxe2x80x9d over to the next lower bit of the test address (e.g., test address=101111111) and is input to the TLB. The test is repeated on the TLB with the 0 being walked through each bit position of the test address, and if a xe2x80x9chitxe2x80x9d (or xe2x80x9cmatchxe2x80x9d) is detected for any of the test addresses then it is determined that the CAM structure has failed.
Such a method of testing typically requires many clock cycles utilizing an off-chip testing program of the prior art. Accordingly, prior art CAM testing methods generally require an undesirably long time, which result in an overall longer production time. Additionally, because such off-chip testing requires a long time, the effective cost associated with producing and testing a chip of the prior art is undesirably high. Not only do prior art. CAM testing programs typically require an undesirably high number of clock cycles to complete, but such off-chip testing programs are typically serial clock tests that operate at approximately 10 megahertz (MHz). Thus, even if the processor speed of a chip is 500 MHz, the CAM testing is performed at approximately 10 MHz. As a result, prior art methods of performing CAM testing require an undesirably long time.
As discussed above, BISTs have been utilized for testing RAM structures of the prior art. However, such RAM BISTs are not readily capable of being implemented for CAM structures. That is, prior art RAM BISTs can not be implemented for CAM structures without making unobvious changes to such prior art RAM BISTs. Generally, RAM BISTs are not easily adapted as CAM BISTs because of the difference in the operation of a RAM structure and a CAM structure. For instance, during operation a RAM structure can typically have data written thereto and read therefrom. Accordingly, a RAM BIST typically writes data to the RAM structure, and then reads the data out of the RAM structure to ensure that the data read out is the same as the data that was written to the RAM.
However, the operation of a CAM structure is much different. That is, memory data can typically be written to a CAM structure, but generally it cannot be read from the CAM structure. Instead, the CAM structure typically receives data and compares it with memory data stored within the CAM. Typically, a CAM does not include circuitry for reading the actual memory data out of the CAM, but instead includes circuitry for comparing received data with the memory data stored therein to determine if a match is made. Because the memory data is not read out of the CAM, testing is typically more complicated for CAM structures than for RAM structures. For instance, testing CAM structures generally involves writing memory data to the CAM and then inputting various test patterns of data to ensure that the CAM structure correctly recognizes whether the input data matches an entry stored in the CAM. Such testing is generally more complex than the relatively simple method of writing memory data in and reading memory data out typically utilized in RAM structures.
Some CAM structures of the prior art include circuitry for reading out memory data That is, some CAM structures of the prior art include circuitry for reading out the actual memory data stored within the CAM. Therefore, the testing of such CAM structures is simplified and may be implemented much like testing methods of RAM structures (e.g., write memory data in and read memory data out). However, some testing is typically required for the CAM""s compare circuitry to ensure that it recognized matches and mismatches in data. Also, the read circuitry implemented for such CAM structures results in an undesirably large amount of additional overhead for implementing such read circuitry. For instance, read circuitry included within such CAM structures increases the cost of implementing the CAMs and increases the amount of surface area consumed by the CAMs. Such overhead is undesirable, especially considering that the read circuitry of the CAM is utilized solely for testing the CAM, and is not utilized during the CAM""s actual operation. Therefore, implementing a CAM structure that includes read circuitry for testing the CAM is generally undesirable.
In view of the above, a desire exists for a BIST for a CAM structure. A further desire exists for CAM BIST that enables a CAM structure to be tested in a timely manner, thereby improving the efficiency of production and testing of a chip that includes a CAM structure. More specifically, a desire exists for a CAM BIST that enables for a CAM structure to be tested easily, quickly, and accurately. Still a further desire exists for a BIST that may be easily implemented for testing a CAM structure, without requiring a large amount of additional overhead for such BIST. That is, a desire exists for a BIST implementation that enables efficient testing of a CAM structure, wherein such BIST implementation does not require a large amount of overhead (e.g., does not require a large amount of additional circuitry for the BIST implementation).
These and other objects, features and technical advantages are achieved by a system and method which provide a BIST for a CAM structure. In a preferred embodiment, an integrated circuit (chip) comprises a CAM structure that is accessible by a processor to satisfy memory access requests. A preferred embodiment further comprises a BIST implemented within such chip, which enables testing the integrity of the CAM structure. In a most preferred embodiment, the BIST is implemented to enable testing a CAM structure that is implemented as a TLB for a cache. However, in alternative embodiments, such BIST may be implemented to test any type of CAM structure. Furthermore, in a preferred embodiment, a BIST may be implemented to not only test the integrity of a CAM structure, but may also be used to test the integrity of a RAM structure.
In a preferred embodiment, a CAM BIST comprises logic capable of generating test values (e.g., a test pattern), a shift register that temporarily stores the test values generated by the logic, and compare circuitry that determines whether a test value matches an entry within the CAM structure. By implementing a BIST for the CAM structure, the CAM structure""s integrity can be tested in a much more efficient manner than is possible utilizing off-chip CAM testing programs of the prior art. For instance, in a preferred embodiment, the number of clock cycles required to perform a CAM test is substantially less than the number of clock cycles required to perform a similar test utilizing an off-chip testing program of the prior art. Furthermore, a preferred embodiment allows for the CAM testing to be performed xe2x80x9cat speed.xe2x80x9d That is, the BIST of a preferred embodiment is capable of testing a CAM structure at the processor speed (e.g., 500 MHz), whereas prior art off-chip testing programs are typically limited to an operating speed of approximately 10 MHz. Accordingly, a preferred embodiment provides a BIST that can be easily implemented within a chip to enable efficient and accurate testing of a CAM structure.
A preferred embodiment provides a BIST for a CAM structure that may be implemented with a minimum amount of circuit overhead. For example, a preferred embodiment may be implemented for testing the integrity of a TLB CAM structure by simply adding a shift register and logic for generating test values. Furthermore, a BIST of a preferred embodiment may be further implemented to be capable of testing not only a CAM structure, but also a RAM structure. Such an implementation allows for both a CAM structure and RAM structure to be tested in an efficient manner utilizing a common BIST, and such a BIST may be implemented with very little circuit overhead.
It should be appreciated that a technical advantage of one aspect of the present invention is that a BIST implementation for a CAM structure is provided. A further technical advantage of one aspect of the present invention is that a CAM BIST implementation is provided, which allows for the integrity of a CAM structure to be tested in an efficient and accurate manner. For instance, in a preferred embodiment, a CAM BIST is implemented that is capable of performing a test in much less clock cycles than required for off-chip CAM tests of the prior art. Furthermore, in a preferred embodiment, a CAM BIST is implemented that is capable of performing a test at the processor clock speed, which may be a much faster speed than is typically utilized for off-chip testing programs. Still a further technical advantage of one aspect of the present invention is that a CAM BIST implementation is provided that requires very little circuit overhead to an existing CAM structure design. Yet a further technical advantage of one aspect of the present invention is that a BIST implementation is disclosed that may be utilized for both a CAM structure and a RAM structure.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.